1. Field of the Invention
The invention relates to an apparatus for processing a packet, a packet communication device, a method of processing a packet, and a computer-readable storage medium containing a set of instructions for causing a computer to carry out a method of processing a packet in a packet processing apparatus.
2. Description of the Related Art
In these days, countermeasures for saving energy are globally studied in order to maintain global environment. Thus, a lot of countries are now preparing for legislation for saving energy and reducing a volume of CO2 emission. It is generally considered that such legislation is directed to energy consumption in traffic, transportation, and production, however, attention is recently paid to an increase in energy consumption in data communication devices and network infra related matters as well as electronic devices such as a computer and a server.
Since an electronic device such as a computer and a server is for a relatively long time in a condition for not carrying out an operation, that is, in a stand-by condition, it is possible to reduce average consumption of electric power by reducing electric power to be consumed in a stand-by condition, contributing to reduction in an equivalent volume of CO2 emission.
Since a data communication device is required to be in a condition in which it is always able to make data communication, although analogue communication was replaced with digital communication, a data communication device is not allowed to be in a stand-by condition unlike an electronic device such as a computer and a server. Accordingly, average consumption of electric power in a data communication device was conventionally reduced by lowering electric power by which a data communication steadily worked.
Thus, reduction in electric power is aimed principally from a standpoint of device technology, specifically, lowering a voltage at which a data communication device works by integrating electronic elements in a higher degree and designing electronic elements in a smaller size.
However, as a result of designing electronic elements in a smaller size, an electronic device can presently operate at 1 volt or lower. Thus, a degree of reduction in a voltage at which electronic elements operate grows dull. Similarly, a degree of reduction in a voltage at which electronic elements operate, caused by higher integration of electronic elements, grows dull. Hence, it is now quite difficult to significantly reduce electronic power consumption in a data communication device.
Furthermore, a design rule in electronic elements is now below 90 nanometers, resulting in an increase in current leakage, which cannot be ignored presently. Though device vendors make attempt to reduce or avoid current leakage, electronic power to be consumed in a data communication device when it is in a stand-by mode is increasing.
Many attempts are made from a standpoint of circuit design. For instance, in a field of a clock synchronization circuit principally used as an internal circuit for electronic parts, an attempt is tried to use a non-synchronization circuit in which a clock signal is not used, to thereby reduce electronic power consumption. Such a non-synchronization circuit brings an advantage of reducing both electric power necessary for steady operation and electric power consumed in a stand-by mode with the result of reduction in average consumption of electric power.
However, there is a problem that, even if a designer would like to choose non-synchronization circuit system for designing a general electronic part such as ASIC and FPGA, tools for designing electronic parts and testing resultants are not yet developed.
FIG. 1 is a block diagram of a related apparatus for processing a packet.
The illustrated apparatus 1000 is comprised of a first packet processing unit 1001, a second packet processing unit 1002, a third packet processing unit 1003, and a clock-signal generator 1004.
The first packet processing unit 1001 receives a packet, and applies a first process to the received packet. A number of clock stages in the first packet processing unit 1001 is S1. After having applied the first process to the packet, the first packet processing unit 1001 transmits the packet to the second packet processing unit 1002.
The second packet processing unit 1002 receives the packet from the first packet processing unit 1001, and applies a second process to the received packet. A number of clock stages in the second packet processing unit 1002 is S2. After having applied the second process to the packet, the second packet processing unit 1002 transmits the packet to the third packet processing unit 1003.
The third packet processing unit 1003 receives the packet from the second packet processing unit 1002, and applies a third process to the received packet. A number of clock stages in the third packet processing unit 1003 is S3. After having applied the third process to the packet, the third packet processing unit 1003 outputs the packet out of the apparatus 1000.
The clock-signal generator 1004 generates a clock signal 1005 having a frequency F, and transmits the clock signal 1005 to the first to third packet processing units 1001, 1002 and 1003.
The first packet processing unit 1001 receives a packet on receipt of the clock signal 1005 from the clock-signal generator 1004. On receipt of the clock signal 1005 from the clock-signal generator 1004, the first packet processing unit 1001 outputs the packet, and simultaneously, the second packet processing unit 1002 receives the packet. Similarly, on receipt of the clock signal 1005 from the clock-signal generator 1004, the second packet processing unit 1002 outputs the packet, and simultaneously, the third packet processing unit 1003 receives the packet. The third packet processing unit 1003 outputs a packet out of the apparatus on receipt of the clock signal 1005 from the clock-signal generator 1004.
In the related apparatus 1000 illustrated in FIG. 1, the clock signal 1005 transmitted to the first to third packet processing units 1001 to 1003 has a fixed frequency F. As a result, the related apparatus 1000 is accompanied with a problem that even if a time interval at which packets are input into the apparatus 1000 varies, for instance, because input traffic volume is lowered, it is not possible to reduce electric power consumed in the apparatus 1000. Specifically, since the first to third packet processing units 1001 to 1003 operate in accordance with the clock signal 1005 having a fixed frequency F, electric power is steadily consumed in a driver for transmitting the clock signal 1005, a wire pattern through which the clock signal 1005 runs and which is dependent on a capacity of the wire pattern, a flip-flop carrying out clocking operation, and/or a part of a clock synchronization memory which operates in dependence on the clock signal 1005, resulting in that electric power consumption is not reduced.
Though the apparatus 1000 illustrated in FIG. 1 is designed to include three packet processing units, an apparatus including a single packet processing unit would be accompanied with the above-mentioned problem.
For instance, Japanese Patent Application Publication No. 2003-158771 has suggested a mobile node making packet-exchange type communication, including a first receiver which receives a packet or a notification signal indicative of arrival of a packet, a second receiver which receives a packet at electric power greater than electric power at which the first receiver receives a packet, and a controller which causes the first receiver to monitor the notification signal or arrival of a packet while a packet is not being received, and causes the second receiver to receive a packet when the first receiver received the notification signal or a packet.
In the suggested mobile node, the first receiver is kept monitoring arrival of a packet, and if the first receiver detected arrival of a packet, the second receiver receives the detected packet, ensuring reduction in electric power consumption in the mobile node. Furthermore, if a packet is not received for a predetermined period of time during the second receiver is in operation, the second receiver is turned off, and the first receiver is turned on, ensuring further reduction in electric power consumption.
However, the above-mentioned mobile node cannot accomplish packet receipt in conformity with packet input traffic. Specifically, the suggested mobile node is designed to turn on one of the first and second receivers merely in dependence on whether a packet is received or not. Thus, the suggested mobile node is accompanied with a problem that the second receiver which receives a packet at electric power greater than electric power at which the first receiver receives a packet operates regardless of packet input traffic, resulting in that it is not possible to effectively reduce electric power consumption.
Japanese Patent Application Publication No. 2004-80326 has suggested an image generator including a network interface having MAC making communication with a network, a data buffer storing data received through the network interface, and a register transmitting a request of changing a frequency to a clock generator. On receipt of data from the network through the network interface, CPU, ASIC and SDRAM starts operating in accordance with a bus clock having a predetermined frequency, transmitted from the clock generator, to output the received data. CPU transfers SDRAM into a self-refresh condition at a predetermined timing through ASIC, and stops operation of ASIC. After CPU transfers into a stand-by mode, the register notifies the clock generator a changed frequency. The clock generator transmits a clock signal having the changed frequency to CPU, ASIC and SDRAM to thereby put the image generator into a power-saving mode.
Japanese Patent Application Publication No. 2004-199139 has suggested a processor system including a plurality of processors, a controller reading commands to be executed by the processors, and selecting a processor(s) in which the commands are executed, and a clock controller controlling a frequency of a clock signal transmitted to the selected processor(s) in accordance with the commands to be executed by the selected processor(s).
Japanese Patent Application Publication No. 2006-279229 has suggested a traffic measuring system including first means for producing and transmitting a plurality of test packets, second means for joining the test packets to user packets transferred in a first direction in a packet communication channel, and separating the test packets from packet rows transferred in a second direction in the packet communication channel, third means for measuring an interval between the test packets separated from the packet rows by the second means, and fourth means for estimating traffic of the user packet, based on the measurement result transmitted from the third means.